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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調(diào)節(jié)ESD保護

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74ALVC74

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 3.6 V

  • CMOS low power dissipation

  • Overvoltage tolerant inputs to 3.6 V

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 250 mA per JESD78 Class II.A

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 to 1.95 V)

    • JESD8-5 (2.3 to 2.7 V)

    • JESD8C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

參數(shù)類型

型號 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Rth(j-c) (K/W) Package name
74ALVC74BQ 1.65?-?3.6 TTL ± 24 2.3 425 low -40~85 103 18.3 71 DHVQFN14
74ALVC74D 1.65?-?3.6 TTL ± 24 2.3 425 low -40~85 103 17.1 62 SO14
74ALVC74PW 1.65?-?3.6 TTL ± 24 2.3 425 low -40~85 138 6.9 65 TSSOP14

封裝

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74ALVC74BQ 74ALVC74BQ,115
(935273692115)
Active ALV74 SOT762-1
DHVQFN14
(SOT762-1)
SOT762-1 SOT762-1_115
74ALVC74D 74ALVC74D,118
(935269741118)
Active 74ALVC74D SOT108-1
SO14
(SOT108-1)
SOT108-1 SO-SOJ-REFLOW
SO-SOJ-WAVE
WAVE_BG-BD-1
SOT108-1_118
74ALVC74PW 74ALVC74PW,118
(935269740118)
Active ALVC74 SOT402-1
TSSOP14
(SOT402-1)
SOT402-1 SSOP-TSSOP-VSO-WAVE
SOT402-1_118

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74ALVC74D 74ALVC74D,112
(935269741112)
Withdrawn / End-of-life 74ALVC74D SOT108-1
SO14
(SOT108-1)
SOT108-1 SO-SOJ-REFLOW
SO-SOJ-WAVE
WAVE_BG-BD-1
SOT108-1_112

環(huán)境信息

型號 可訂購的器件編號 化學(xué)成分 RoHS RHF指示符
74ALVC74BQ 74ALVC74BQ,115 74ALVC74BQ rohs rhf rhf
74ALVC74D 74ALVC74D,118 74ALVC74D rohs rhf rhf
74ALVC74PW 74ALVC74PW,118 74ALVC74PW rohs rhf rhf

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號 化學(xué)成分 RoHS RHF指示符
74ALVC74D 74ALVC74D,112 74ALVC74D rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (18)

文件名稱 標(biāo)題 類型 日期
74ALVC74 Dual D-type flip-flop with set and reset; positive-edge trigger Data sheet 2024-02-05
AN90063 Questions about package outline drawings Application note 2025-06-13
mna420 Block diagram: 74ALVC74BQ, 74ALVC74D, 74ALVC74PW, 74LVC74ABQ, 74LVC74AD, 74LVC74ADB, 74LVC74APW Block diagram 2009-11-03
SOT762-1 3D model for products with SOT762-1 package Design support 2019-10-03
SOT108-1 3D model for products with SOT108-1 package Design support 2020-01-22
SOT402-1 3D model for products with SOT402-1 package Design support 2023-02-02
alvc74 alvc74 IBIS model IBIS model 2013-04-08
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
DHVQFN14_SOT762-1_mk plastic, dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; 0.5 mm pitch; 2.5 mm x 3 mm x 0.85 mm body Marcom graphics 2017-01-28
SO14_SOT108-1_mk plastic, small outline package; 14 leads; 1.27 mm pitch; 8.65 mm x 3.9 mm x 1.75 mm body Marcom graphics 2017-01-28
TSSOP14_SOT402-1_mk plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body Marcom graphics 2017-01-28
SOT762-1 plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 14 terminals; 0.5 mm pitch; 2.5 x 3 x 1 mm body Package information 2023-04-05
SOT108-1 plastic, small outline package; 14 leads; 1.27 mm pitch; 8.65 mm x 3.9 mm x 1.75 mm body Package information 2023-11-07
SOT402-1 plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body Package information 2023-11-07
SO-SOJ-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
SO-SOJ-WAVE Footprint for wave soldering Wave soldering 2009-10-08
WAVE_BG-BD-1 Wave soldering profile Wave soldering 2021-09-08
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

如果您需要設(shè)計/技術(shù)支持,請告知我們并填寫 應(yīng)答表 我們會盡快回復(fù)您。

模型

文件名稱 標(biāo)題 類型 日期
SOT762-1 3D model for products with SOT762-1 package Design support 2019-10-03
SOT108-1 3D model for products with SOT108-1 package Design support 2020-01-22
SOT402-1 3D model for products with SOT402-1 package Design support 2023-02-02
alvc74 alvc74 IBIS model IBIS model 2013-04-08

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